With the increasing complexity of integrated circuit (e.g., semiconductor) devices, the quality of the wafers upon which the integrated circuits are positioned may be significant. Wafer quality is typically important in achieving desirable device yield and reliability.
Conventional wafer quality usually depends on a number of factors. For example, the quality is often influenced by the quantity of defects present in the wafer. Defects are typically generated during crystal growth. The wafer defects may generally be divided into two types: (1) defects arising from particle contamination and (2) crystal defects originating from silicon ingot growth.
During typical semiconductor wafering processes, single crystal silicon is usually formed by employing a multi-step process on a raw material such as quartzite, for example. The raw material may then be grown into a single crystal ingot by a suitable technique such as a Czochralski (CZ) method or a Float Zone (FZ) method.
An array of patterning and polishing processes are then typically carried out on the grown single crystal ingot. A wafer designed for use in an integrated circuit device is subsequently formed. In particular, the surface of the single crystal ingot is typically trimmed down in attempting to achieve proper size and morphology. After the ingot surface is examined, typically by an x-ray technique, the trimmed ingot may then be adjusted for orientation flattening along the lengthwise direction of the ingot. Typically, ingot etching is subsequently performed in order to potentially remove contaminants which may exist on the ingot surface. The ingot may then be sawed to form silicon slices or wafers. An edge-rounding technique can next be carried out on the edge of the silicon wafers, and a lapping technique may thereafter be performed on the wafer to minimize wafer bending. Contamination which may be present on the slice can be removed by employing a suitable chemical etching technique such as, slice etching, for example.
Next, the wafer is usually subjected to a thermal processing technique known as "donor killing". The "donor killing" process is designed to prevent interstitial oxygen from serving as a donor subsequent to ingot growth. The process is intended to minimize any complications with respect to wafer electrical control that may result in an integrated circuit device.
After the donor killing process, the surface of the wafer is typically polished and cleaned by chemical or mechanical means. Defects or orientations which may be present in the wafer can then be examined. The wafer is then typically subjected to an inspection and, if acceptable, the wafer is packaged for commercial use.
A conventional cleaning process, however, may be limited in the types of contaminants and impurities that it can remove. More particularly, although contaminants such as dust may be removed, potential faults in the wafer like D-defects, oxygen precipitates, stacking faults, and metallic precipitates may not be addressed by the above cleaning process.
Potentially troublesome defects include, for example, COPs ("Crystal Oriented Particles") known as micropits, along with D-defects. As known in the art, "D-defects are defined as deformation defects, namely defects that propagate three-dimensionally so as to disrupt the crystal lattice structure. These defects often adversely affect the yield and reliability of integrated circuit devices, since the defects can impact manufacturing processes involved in producing the devices. Thus, it is typically important to examine the density and deflection distribution of the wafer surface, along with the morphology of the surface. Based on these analyses, adjustments may be made which can allow for increases in device yield prior to a device being used in a wafer.
A conventional method for examining potential wafer surface defects involves laser scattering particle counter (LSPC) technology. In the above method, a bare wafer is typically cleaned with, for example, a solution of SC1 (i.e., ammonium hydroxide, hydrogen peroxide, and water having a molar ratio of 1:1:8 respectively), along with hydrogen fluoride. Subsequently, a constant wavelength laser is typically irradiated on the bare wafer by a laser scattering particle counter. Scattered signal data is then typically generated. As a result, the surface defects of the wafer may be examined.
There are potential problems associated with the above method. First, it is often difficult to accurately measure the amount and distribution of COPs on a wafer. More particularly, COPs are typically found only on the vacancy-rich area of the wafer. As a result, it is often necessary to measure the real diameter of the vacancy-rich area from a COP map acquired by a laser scattering particle counter. When a bare wafer is cleaned with a SC1/hydrogen fluoride solution, however, it may be difficult to distinguish real contamination from the COPs. Moreover, particles often accumulate on defects during COP mapping, and the presence of the particles may distort the level of defects measured from the wafer. Second, it may be difficult to fully detect the defects due to limitations in the conventional scattering particle counters. A conventional scattering particle counter usually has a detection limit of 0.12 .mu.m, and as a result COPs of smaller size may not be observed. Since smaller defects are often found in the peripheral regions of vacancy-rich areas in the wafer, it may be extremely difficult to accurately measure the diameter of the vacancy-rich area. Third, a conventional scattering particle counter technique is often unable to accurately access the size and morphology of wafer defects and, as a result, their position on the wafer surface. Conventionally, defect position is usually observed via the coordination between a LSPC technique and an AFM (atomic force microscope) technique. Nonetheless, the size and defects determined by using an AFM technique may be larger than the size and defects measured by the LSPC technique. Thus, the size, morphology, and location of the defects may not be accurately determined.
There remains a need in the art to address the potential difficulties associated with conventional methods of analyzing wafer defects.